As technology moves into nano-scale Complementary Metal Oxide Semiconductor (CMOS), analog Phase Locked Loop (PLL) design faces more and more challenges attributed to device matching, reduced output impedance, and low supply voltage. Digital PLLs (DPLLs) may sometimes replace analog PLLs, but generally suffer from low jitter performance i.e., high jitter at the output of the PLL.
PLLs employ phase frequency detectors (PFDs). A PFD compares a reference clock signal with a feedback clock signal to determine whether to increase the frequency of an oscillator of the PLL, reduce the frequency of the oscillator, or keep the frequency of the oscillator constant. The output of the PFD includes phase error even when the reference clock signal and the feedback clock signal are aligned. This phase error of the PFD may add jitter to the output clock of the PLL, and so may reduce PLL performance.